Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays (Computer Systems Series)

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About Fault Tolerance Through Reconfiguration In VLSI And

Fault tolerance is one of the principle mechanisms for achieving high reliability, high availability in digital systems. It is the survival attribute of digital systems. This book brings together and discusses the most significant results scattered across the vast field of research in fault tolerance. It focuses in particular on reconfiguration techniques and presents the authors' own results in the reconfiguration of processing arrays. By means of dedicated arrays, they note, it is possible to build systems that are orders of magnitude more powerful than programmed computers. Their treatment of networks and arrays is extensive and has wide applicability. Contents: Introduction. Typical Processing Arrays. Failure Mechanisms and Fault Models. Basic Problems of Fault-Tolerance Through Array Configuration. Technologies Supporting Reconfiguration Testing. Reconfiguration: An Introduction. The Diogenes Approach. Reconfiguration for Linear Arrays. Graph-Theoretical Approaches to Reconfiguration. Local Reconfiguration. Global Reconfiguration Techniques: Row/Column Elimination. Global Mapping: Index Mapping Reconfiguration Techniques. Reconfiguration Based on Request-Acknowledge Local Protocols. Reconfiguration of Multiple-Pipeline Structures. Some Extensions Toward Time Redundancy. Appendix: Reliability Prediction of Arrays. R. Negrini, M. G. Sami, and R. Stefanelli are researchers at the Politecnico di Milano. Fault Tolerance Through Reconfiguration in VLSI and "I Arrays is included in the Computer Systems series, edited by Herb Schwetman.