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High Level Synthesis of Pipelined Datapaths
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About High Level Synthesis Of Pipelined Datapaths
Product Description The CAD tool PIPE has been developed in response to the increased speed requirement and complexity of ASIC executable tasks. High level synthesis offers more complex ASIC design solutions, now emerging in academic and industrial design environments. In this timely resource, the applicability of the PIPE tool is considered in the context of the field towards hardware / software co--design and system level synthesis. * Increasing interest in high-level logic synthesis as designs with 200 million transistors on a single chip become commonplace * Step-by-step tutorial in the CAD tool "PIPE", illustrating the applications potential, including the advantages, drawbacks and benchmark results * Supplementary CD-ROM including synthesis subroutines and benchmarks Professional hardware engineers and researchers who are familiar with high level synthesis or related topics would find this to be a valuable reference resource. Also, MSc and PhD students studying or researching high level synthesis or related topics could use the book as a tutorial text to accompany existing works on this rapidly evolving topic. From the Inside Flap The pipelined mode of data processing has been developed in response to the growing complexity and increased speed requirement of ASICs (application specific integrated circuits). Providing an insight into the High Level Synthesis (HLS) algorithms used for the pipelined datapaths of hardware components, the book illustrates these methodologies in hardware/software co-design and system level synthesis. Features include: * The unique CAD tool, PIPE, which performs and illustrates all the basic HLS steps suited to work on pipelined datapath designs. * Accompanying CD ROM featuring a step-by-step PIPE tutorial, yielding an allocated structural description of the pipelined datapath. * Models and methods for solving HLS problems, including illustration of the applications potential, advantages, drawbacks and benchmark results of PIPE. * Descriptions of the relevant control principles and the unique handling of multiple-process recursive loops. * Thorough coverage of the basic algorithms for data dominated structures, such as scheduling, allocation, buffer insertion, replication of operations and synchronisation. This accessible guide to high level synthesis will appeal to advanced students in electrical engineering and computer science. Hardware engineers and designers using pipelined datapaths and logic synthesis will also find this an indispensable aid. From the Back Cover The pipelined mode of data processing has been developed in response to the growing complexity and increased speed requirement of ASICs (application specific integrated circuits). Providing an insight into the High Level Synthesis (HLS) algorithms used for the pipelined datapaths of hardware components, the book illustrates these methodologies in hardware/software co-design and system level synthesis. Features include: * The unique CAD tool, PIPE, which performs and illustrates all the basic HLS steps suited to work on pipelined datapath designs. * Accompanying CD ROM featuring a step-by-step PIPE tutorial, yielding an allocated structural description of the pipelined datapath. * Models and methods for solving HLS problems, including illustration of the applications potential, advantages, drawbacks and benchmark results of PIPE. * Descriptions of the relevant control principles and the unique handling of multiple-process recursive loops. * Thorough coverage of the basic algorithms for data dominated structures, such as scheduling, allocation, buffer insertion, replication of operations and synchronisation. This accessible guide to high level synthesis will appeal to advanced students in electrical engineering and computer science. Hardware engineers and designers using pipelined datapaths and logic synthesis will also find this an indispensable aid. About the Author Péter Arató is the author of High Level Synthesis of Pipelined D
